1. Field of the Invention
The present invention relates to semiconductor fabrication methods and structures and, more particularly, to a method and structure of fabricating memory device with dual spacers in cell and periphery region.
2. Description of Related Art
Integrated circuits are well known. Integrated circuits are commonly used to make a wide variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits, so as to increase the density of the individual components thereof and consequently enhance the functionality of an integrated circuit. As device densities increase with reduced feature width, the aspect ratio also increases. However, higher aspect ratios resulting from formation of features on a substrate separated by small gaps, can reduce the effective process windows for etching processes and deposition processes. For example, the interlayer dielectric layer gap fill-in process and silicide deposition process windows in the memory cell region on an integrated circuit memory reduce as device densities and aspect ratios increase for memory cell gate features that result in the gaps.
In addition, for devices with plural circuit regions, such as memory devices, the circuit regions may have different performance requirements that are reflected in the manufacturing processes. In memory devices, for example, the memory cell region requires high reliability and high density, while some circuits in the periphery require high breakdown voltage. One common process used in integrated circuit manufacturing for formation of small features is known as the sidewall spacer. Sidewall spacers are used to define features, by the width of the spacer, with widths possible that are less than the minimum feature width of the lithography process. However, the features defined using sidewall spacers for one region in an integrated circuit may not be useful in another region due for example, to different performance requirements in the different regions.
There is a need for a method and structure to achieve these different performance requirements in memory chips and other integrated circuit devices having multiple circuit regions.